BE (Electronics And Communication Engineering), Thanthai Periyar Govt. Institute of Technology, Vellore

ME (Embedded System Technologies), Anna University Coimbatore

Digital signal processor architecture and algorithms - In general, the performance of a circuit depends on circuit depth i.e., the maximum number of levels in the topological sort, circuit size (area) i.e., the number of combinational elements and net power requirement. The careful optimization in these parameters will ensure the highest performance. The major objective of the research work is to improve the performance of VLIW Digital Signal Processor which includes the functional units like fixed/floating point adder/subtractor, multiplier/MAC, CORDIC, transform unit and etc.

(1) Mohamed Asan Basiri M and Noor Mahammad Sk, “An Efficient Hardware Based MAC Design in Digital Filters with Complex Numbers”, IEEE International conference on signal processing and integrated networks (SPIN), pp. 475-480, Feb. 2014, Noida.

(2) Mohamed Asan Basiri M, Samaresh Chandra Nayak and Noor Mahammad Sk, “Multiplication Acceleration Through Quarter Precision Wallace Tree Multiplier”, IEEE International conference on signal processing and integrated networks (SPIN), pp. 502-505, Feb. 2014, Noida.

(3) Mohamed Asan Basiri M and Noor Mahammad Sk, “An Efficient Hardware Based Higher Radix Floating Point MAC Design”, ACM Transactions on Design Automation of Electronic Systems, 20, 1, Article 15 (November 2014), 25 pages. (SCI)

(4) Mohamed Asan Basiri M and Noor Mahammad Sk, “Memory Based Multiplier Design in Custom and FPGA implementation”, Springer International Symposium on Advances in Intelligent Systems and Computing, Vol. 320, pp 253-265, Sep. 2014, India.